Part 1: Getting started
Installation, Tests & Basic information.

1. Which sampling frequencies can I reach with the ADACMaster I?
2. Is there a data transfer rate limitation between the ADACMAster and the FPGA due to the VIM interface Bi-FIFO's that connects the VIM sites to the FPGA?
3. I just received my ADACMaster module and I would like to check if its working correctly. Do you have a suggested test procedure?
4. I am using an ADACMaster together with FPGALink, is there a quick test I can do to test the ADC-FPGA-DAC loop?
5. I want to use ADACMaster with Simulink, but I don't know how to procede. Can you give me a starting point?

Part 2:
Using the ADACMaster with DSPLink and FPGALink

1. I am using the ADACMaster blockset in my design. I did "Build" my model using MATLAB but I don't see any signal at the ADACMaster output. Is it an error in my model?
2. I am using ADACMaster and FPGALink and I want to perform data processing in the DSP. I have made my DSP and FPGA models and was able to build the .bit for the FPGA and the .out for the DSP without problem. However, the results I see in the simulink scope of my DSP model are not like I expected. Where could be the problem?
3. I want to process data acquired by the ADACMaster and feed it to the CODEC in real-time after having done down-sampling? Is it possible to implement this kind of design synchronously?
4. In my FPGALink model, I use VIM Gateway in both Read and Write mode. In my DSPLink model, I have set both ADACMaster Acquisition and Transmission blockset to use 64 MHz fix clock Oscillator. Are these two clock synchronous?

Possible sampling frequencies depends on the type of FPGA you are using.

XC2V and XCVE FPGAs can sample at up to 75 MHz per node. In other words, this means that it is possible to use an ADC Fs of 65MHz and a DAC Fs of 75 MHz in r/w (full duplex) mode

XCV300 & XCV800 FPGAs can sample at up to 37.5 MHz in R or W only mode. In full duplex mode, 37.5 MHz can be dispatched such as:

• 18.75MHz (ADC) -18.75 (DAC)
• 25 MHz (ADC) - 12.5 MHz (DAC)
• etc...

Take note that Virtex I (xcv300, xcv800) C6xx-based SignalMaster are obsolete and can no more be purchased.

Virtex 2 FPGA Series provide dedicated on-chip blocks of 4096 bytes dual-port synchronous RAM, which are ideal for use in FIFO applications. In our case, using these blocks allows a FIFO implementation that runs at 170MHz.

Two bus are used on the VIM Bi-FIFO interface, both are 32 bits size. One of them is used for acquisition channel (ADC) A & B and the other is used for transmission channel (DAC) A & B. As one FIFO has a capacity of 170MHz x 4 bytes (32 bits) = 680 MBytes (1360MBytes for the two Bus), there is no problem in implementing ADC and DAC at 65MHz (260MBytes).

Moreover, it is also easily able to handle the maximum capacity of the ADACMaster, which is 65MHz ADC and 125MHz DAC = 380MBytes.

There is a test procedure for ADACMaster input (ADC) and output (DAC) stages described in our ADACMaster QuickStart Guide.

You should have receive this guide with your ADACMaster software.

If you don't have it, contact Lyrtech support.

Using the ADACMaster Demo accessible from MATLAB Demo Window (LSP FPGALink) is the fastest solution to test the ADC-FPGA-DAC loop because this demo performs a simple loopback in the FPGA.

There are two ways to use the ADACMaster: frame shot and real-time.

Frame shot mode: (DSPLink required)
In Frame shot mode, you acquire frames of data coming from the ADC and based on a frame size you can specify in the ADACMaster Acquisition block. You only need a DSP model to use ADACMaster in frame-shot mode. See ADACMaster Test and FFT demos examples of frame shot demos. Note that it is impossible to use the DAC in frame shot mode.

Real-Time mode: (DSPLink and FPGALink required)
Two Simulink models are required if you wish to use the ADACMaster for real-time signal processing. One of them is intended for the FPGA (an FPGALink model using VIM Gateway block to access ADACMaster's I/Os) and the other for the DSP (DSPLink model using ADACMaster blockset to control ADACMaster parameters). See ADAC demo FPGA & DSP for an example of real-time demo in the LSP FPGALink demos section.

This being said, there is one thing to remember before beginning the design of a system using the ADACMaster: if real-time signal processing is to be done, then an FPGA model must be created. More details about real-time models are provided in the upcoming questions highlighting the important aspects to consider in case of a mixed FPGA/DSP hardware implementation.

Before changing anything in your model, it is very important to check if the ADCs are enabled. To do this, build your model, connect to the SignalMaster, open ADAC Master Acquisition CTRL block and select the ADCs Run State parameter (reset it if it was already selected).

If you still have nothing at the output, please test your ADACMaster according to our test procedure described earlier.

AA very important thing to consider when working with mixed FPGA/DSP hardware implementation is the significant gap in terms of processing speed between the two components. Effectively, the FPGA can easily handle a 50 MHz signal while the DSP, being clocked at 150 MHz, would have only 3 cycles to perform his algorithm, which is insufficient. That is, if the data is coming too fast for the DSP to be able to perform his algorithm, we say that the DSP is "overrunning".

An effective way to see if the DSP is overrunning is to use the Profiler block (from the demos window, see LSP FPGALink/ MultiRate FIR Filter demo for an example) to monitor the DSP load required by the algorithm.

This being said, the best solution to avoid DSP overrunning is to use the FPGA to perform signal decimation (or down-sampling) before transferring data to the DSP.

Yes, this kind of design is now possible since the releasing of FPGALink 3.1.02. This design implies the usage of a synchronous clock which must be propagated in the following way: ADAC-FPGA-DSP-CODEC

The two following sections will explain how to implement such a design by designing a FPGALink model and a DSPLink model.

FPGA MODEL:
The first think to consider while implementing this design is to use the VIM clock NODE B (VIM Clock Node A should not be used with the ADACMaster) as LSP FPGA Generator Real-time clock source. This will permit to use the ADACMaster's clock (Programmable clock, Fixed Oscillator or External Clock) as the FPGA real-time clock.

The second thing in order to send data to the CODEC by the way of the BUS Gateway is to use the CODEC Sync Block which is accessible from the Simulink Library Browser: LSP FPGALink Blockset/ FPGA-Based Blockset/ CODEC Sync. This block will force the CODEC to use a clock synchronous to the ADAC and the FPGA instead of using it's default 12.288 MHz clock. If you select the following clock (75 MHz, 25 MHz, or 12.288 MHz) as LSP FPGA Generator Real time Clock Source, the Codec Sync block will enter its Real-Time Clock frequency when the user will press CTRL+D. If the user chooses VIM Node B as LSP FPGA Generator Real time Clock Source, then the user will need to enter himself the value of the VIM clock feeded to the FPGA. To enter the desired CODEC Sample Rate, enter some value as the Sample Period of the CODEC Sync block. If the Sample Rate corresponding to the Real time clock Frequency divided by the Sample Period is valid, then this value will be entered in the CODEC Sync block as the CODEC Sample Rate. If the value computed is not valid, some error message will appear showing the possible Sample Period which can be entered.

Once the Codec Sync's Sample Rate Parameter is computed, the user should then put some XILINX DownSample Block for which the downsampling value should correspond to the Sample Period entered in the CODEC Sync block.

The user can then use the Bus Gateway to feed the Data to the DSP. The Bus Gateway is preferred over the MCBSP Gateway in this case since the MCBSP Gateway can not be clocked synchronously with the FPGA while using the VIM Node B as LSP FPGA Generator Real time Clock Source.

The user can now generate his bitstream. During the process, some customized CS4228_ctrl block will be generated . This block should be the one used by the user while designing his DSP Model as we will see in the next section.

DSP MODEL:
The first thing to set in the DSP Model is the ADACMaster Acquisition and Transmission CTRL Acquisition Clock source parameter and Transmission Clock source parameter. The value of these clock must be set accordingly to the one set in the FPGALink CODEC Sync block Real-time clock frequency parameter. Take note that the ADACMaster Transmission CTRL block must be used because the FPGA design uses the VIM Node B as LSP FPGA Generator Real time Clock Source

The user should then use the Codec_ctrl block generated during the FPGA bitstream process in his DSP model in order to use the desired clock and configuration.

The user can refer to the ADAC Acquisition and CODEC demo for some example about CODEC synchronisation. This demo can be accessed in the following section by typing demos at the Matlab prompt:

>> demos

In the following section:
LSP FPGALink /Viretx II demos/ADAC Acquisition and CODEC (DSP & FPGA)

The node location refers to the electrical and physical location of the ADCs and DACs. On the ADACMaster, both ADCs are located on the node A while both DACs are located on the node B. On the ADACMaster module, there is one crystal at 64 MHz, one programmable clock and one external clock. Each of these clock is physically connected to the ADCs and DACs. Thus, when using the 64 MHz crystal, the ADC and DAC will be running synchronously.